Memory devices are typically provided as internal, semiconductor, integrated circuits in computers, personal digital assistants (PDAs), digital cameras, and cellular telephones, among various other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. In the NOR array architecture, the floating gate memory cells of the memory array are typically arranged in a matrix. The control gates of each floating gate memory cell of the array matrix are typically coupled by rows to access lines, e.g., word lines, and their drains are coupled to data lines, e.g., bit lines. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells (i.e., those cells whose control gates are commonly coupled) by selecting the access line coupled to (and, in some cases, forming) their gates. The row of selected memory cells then place their data values on the data lines (wherein the cells commonly coupled to a particular data line are referred to as a “column”) by flowing different currents depending on if a particular cell is in a programmed state or an erased state.
A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the control gates of each floating gate memory cell of the array are coupled by rows to access lines. However, each memory cell is not directly coupled to a data line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a data line.
Flash memory cells can be programmed to a desired state. That is, electric charge can be placed on, or removed from, the floating gate of a memory cell to put the cell into any of a number of stored states. For example, a single level cell (SLC) can represent two states, e.g., a 1 or 0 state, such as to indicate a binary digit (“bit”). Flash memory multilevel memory cells, which can be referred to as multi-bit cells, or multi-state cells, can be programmed into more than two possible states, e.g., to store more than one bit of data per cell. MLCs allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. As an example, MLCs can have a number of program states and an erase state, e.g., a cell capable of representing four bits can have fifteen program states and an erase state, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 1110, 1000, 1010, 0010, 0110, and 0000.
Program/erase cycling is one factor which can affect memory cell performance. Cycle endurance of a memory cell is dependent on the difference in a cell's threshold voltage, Vt, between the programmed state and the erased state. As the number of program/erase cycles increases, i.e., cycle endurance, cell current can decrease in some memory cells, resulting in subsequent data read errors. Increasing program/erase cycling is also associated with changes in memory performance, e.g., programming speed decreases and erase speed increases, as well as other changes in operational attributes. Slower programming speed may make the affected cells more susceptible to over-programming. For instance, when a voltage is applied to a particular cell, the conditioning of the cell may cause the cell to be over charged, thereby causing further cell degradation and an incorrect result when read and/or verified.